The present invention related to semiconductor devices and methods for fabricating a semiconductor device, and more particularly relates to a semiconductor device used for protecting an internal circuit from electrostatic destruction and a method for fabricating the same.
In a semiconductor device, signals are transmitted and received between an internal circuit and the outside of the device via an input/output pad. From the input/output pad to the internal circuit, not only signals for driving the internal circuit but also static electricity unexpectedly generated outside of the device is supplied. When large static electricity is supplied to the internal circuit, elements provided in the internal circuit may be damaged.
To avoid such electrostatic destruction of the internal circuit, an electrostatic protection device or an electrostatic protection circuit including an electrostatic protection device are provided between an internal circuit and an input/output pad in a semiconductor device. As a widely used electrostatic protection device, a parasitic bipolar transistor having the source (S)xe2x80x94substrate (B)xe2x80x94drain (D) structure for an MISFET is known.
Hereinafter, the structure of an electrostatic protection device will be described with reference to FIG. 9. FIG. 9 is a cross-sectional view schematically illustrating the structure of a known semiconductor device using an npn type parasitic bipolar transistor.
As shown in FIG. 9, in the known semiconductor device, provided are an internal circuit 81 and an input/output pad 82 which allows signal transmission and reception between the internal circuit 81 and the outside of the semiconductor device, an electrostatic protection device 83 connected between the internal circuit 81 and the input/output pad 82 and having an n-type MISFET structure. The electrostatic protection device 83 includes a semiconductor substrate 90, source and drain regions 91 and 92 provided in the semiconductor substrate 90 so as to be spaced apart from each other, a source electrode 93 provided on the source region 91, a drain electrode 94 provided on the drain region 92, a gate insulating film 95 provided on the semiconductor substrate 90, a gate electrode 96 provided on the gate insulating film 95, a sidewall spacer 97 provided on each of the side faces of the gate insulating film 95, and a resistance 98 connected to the gate electrode 96.
The drain electrode 94 of the electrostatic protection device 83 is connected between the internal circuit 81 and the input/output pad 82. Meanwhile, the gate electrode 96, the source electrode 93 and the semiconductor substrate 90 are connected to a ground potential 99 to be grounded. When the electrostatic protection device 83 functions as a parasitic bipolar transistor, the drain region 92 serves as a collector 101, the source region 91 serves as an emitter 100, and a region of the semiconductor substrate 90 located between the source and drain regions 91 and 92 serves as a base 102. Note that a substrate resistance 104 is illustrated in FIG. 9 to schematically show that the semiconductor substrate 90 functions as a resistance when the electrostatic protection device 83 functions as a parasitic bipolar transistor.
Next, the operation mechanism of the electrostatic protection device 83 will be described with reference to FIG. 9. When an excessive negative voltage caused by static electricity is applied from the outside of the semiconductor device to the input/output pad 82, an electric current flows from the ground potential 99 in the direction toward the input/output pad 82 so that static electricity is discharged. The electric current flows according to forward characteristics of a pn junction formed by the n-type drain region 92 of the semiconductor substrate 90 and a p-type region of the semiconductor substrate 90 connected to the ground potential 99. Thus, the excessive negative voltage applied to the input/output pad 82 is clamped. Therefore, the internal circuit is protected from the excessive voltage.
On the other hand, when an excessive positive voltage is applied to the input/output pad 82, the operation mode of the electrostatic protection device 83 is turned from an MISFET mode to a bipolar transistor mode. This operation will be specifically described hereinafter. When an excessive voltage is applied from the input/output pad 82 to the drain electrode 94, an electric current flows to the ground potential 99 via the drain electrode 94, the semiconductor substrate 90 and the source electrode 93 so that static electricity is discharged. As the voltage applied to the drain electrode 94 is increased, impact ionization is accelerated at the edge of drain region 92 of the n-type MISFET and therefore a substrate current 103 is gradually increased. When the substrate current 103 flows in the substrate resistance 104, a voltage drop occurs to increase the potential of the base 102. When the base potential is increased to a certain extent, the parasitic bipolar transistor is conducted so that a large current flows from the collector 101 (i.e., the drain region 92) to the emitter 100 (i.e., the source region 91). A voltage applied to the drain to turn the operation mode of the electrostatic protection device from the operation mode as an MISFET to the operation mode as a bipolar transistor is called xe2x80x9ctrigger voltage.xe2x80x9d
FIG. 10 is a graph showing the relation between the voltage level and the current level in a transistor exhibiting a snap-back characteristic. In the electrostatic protection device 83, a current flows according to the snap-back characteristic shown in FIG. 10. Thus, a voltage applied to the drain electrode 94 is suppressed lower than the trigger voltage. Normally, the trigger voltage is lower than the breakdown voltage of the internal circuit device and therefore the internal circuit is protected from an excessive voltage.
Note that the resistance 98 of FIG. 9 has the effect of reducing the trigger voltage. The principle of the effect will be described hereinafter. In general, the drain region 92 of the MISFET is formed so as to overlap with an edge portion of the gate electrode 96. Thus, a capacitance exists between the gate and the drain. When an excessive positive voltage caused by static electricity is applied to the drain electrode 94 with the capacitance formed, a charge current generated due to the capacitance momentarily flows from the drain electrode 94 to the ground potential 99 via the gate electrode 96 and the resistance 98. Accordingly, a voltage drop by the resistance 98 occurs and thus the potential of the gate electrode 96 is increased. When the potential of the gate electrode 96 is increased, the current flowing between the drain and the source is increased, thus accelerating impact ionization. Therefore, the substrate current 103 is increased, and thus a large voltage drop by the substrate resistance 104 occurs to increase the base potential. As a result, the parasitic bipolar transistor is easily conducted. As has been described, with the resistance 98 provided, the level of a trigger voltage when an excessive positive voltage caused by static electricity is applied can be reduced.
Note that the above-described electrostatic protection device was disclosed in Japanese Unexamined Patent Publication No. 3-73567.
In the known semiconductor device, however, the following problems arise.
Generally, MISFETs are designed so that deterioration of the gate insulating film therein due to injection of hot carriers is suppressed. More specifically, in MISFETs, impurity profiles are formed so that an electric field at the edge of the drain can be relaxed. Accordingly, the substrate current generated through impact ionization is reduced and thus the voltage drop by a substrate resistance is reduced. This results in an increase in the trigger voltage. Therefore, it becomes difficult to have a parasitic bipolar transistor conducted.
Moreover, in recent years, the thickness of a gate insulating film in an MISFET for an internal circuit has been reduced to 3 nm or less. Also, the gate breakdown voltage is reduced to 10 volt or less.
Therefore, when with a high trigger voltage, an excessive positive voltage caused by static electricity is applied to a semiconductor device, a higher voltage than the breakdown voltage is applied to a gate insulating film in an internal circuit used for the MISFET. This may cause destruction of the gate insulating film.
It is therefore an object of the present invention to devise a measure for effectively reducing a trigger voltage in a transistor exhibiting a sna-back characteristic and thereby provide a highly electrostatic protective semiconductor device and a method for fabricating the same.
A semiconductor device according to the present invention is characterized by comprising: a semiconductor layer; a source region provided in the semiconductor layer; a drain region provided in the semiconductor layer so as to be spaced apart from the source region; a gate insulating film provided on the semiconductor layer; a gate electrode provided on the gate insulating film; a first interlevel insulating film provided on the semiconductor layer so as to cover the gate electrode; a first gate interconnect provided on the first interlevel insulating film so as to be electrically connected to the gate electrode; a first drain interconnect provided on the first interlevel insulating film so as to be electrically connected to the drain region; and a second interlevel insulating film formed on the first interlevel insulating film so as to cover the first gate interconnect and the first drain interconnect, wherein part of the first gate interconnect extends in the gate width direction so that the part of the first drain interconnect and part of the first gate interconnect face each other with part of the second interlevel insulating film interposed therebetween.
Thus, a capacitance can be held between the first gate interconnect and the first drain interconnect, resulting in reduction in the trigger voltage. Therefore, a parasitic bipolar transistor can be easily conducted.
If the inventive semiconductor device further includes a second drain interconnect provided on the second interlevel insulating film so as to be electrically connected to the first drain interconnect, the drain region and members located outside of the semiconductor device can be electrically connected to each other by the second drain interconnect.
If the thicknesses of the first drain interconnect and the first gate interconnect are larger than that of the second drain interconnect, a larger capacitance can be held.
If the part of the second interlevel insulating film interposed between the parts of the first drain interconnect and the first gate interconnect is formed of a high dielectric material, a larger capacitance can be held.
It is preferable that the high dielectric material is silicon nitride.
If the inventive semiconductor device further includes a second gate interconnect provided on the second interlevel insulating film so as to be electrically connected to the first gate interconnect; and a third interlevel insulating film provided on the second interlevel insulating film so as to cover the second drain interconnect and the second gate interconnect and in the inventive semiconductor device, parts of the second drain interconnect and the second gate interconnect extend so as to face each other, a larger capacitance can be held.
If the part of the third interlevel insulating film interposed between the parts of the second drain interconnect and the second gate interconnect is formed of a high dielectric material, a larger capacitance can be held.
It is preferable that the high dielectric material is silicon nitride.
If the inventive semiconductor device further includes a first source interconnect provided on the first interlevel insulating film so as to be electrically connected to the source region and in the inventive semiconductor device, the distance between the first source interconnect and the first gate interconnect is greater than that between the first drain interconnect and the first gate interconnect, the distance between the first drain interconnect and the first gate interconnect is smaller than that in a known semiconductor device. Therefore, a capacitance can be more effectively held between the first drain interconnect and the first gate interconnect.
If the drain region is electrically connected to the internal circuit and the input/output terminal that can input a signal into the internal circuit, it is possible to prevent destruction of the internal circuit even with an excessive voltage caused by static electricity applied to the input/output terminal.
It is preferable that the gate electrode is electrically connected to the resistance.
A method for fabricating a semiconductor device according to the present invention includes: the step a) of forming a gate electrode on a semiconductor layer with a gate insulating film interposed therebetween; the step b) of forming source and drain regions in the semiconductor layer; the step c) of forming a first interlevel insulating film over the semiconductor layer after the step b); the step d) of forming a first gate interconnect on the first interlevel insulating film so as to be electrically connected to the gate electrode and extend in the gate width direction; the step e) of forming a first drain interconnect on the first interlevel insulating film so as to be electrically connected to the drain region and have part facing part of the first gate interconnect in the gate width direction; and the step f) of forming a second interlevel insulating film on the first interlevel insulating film so as to cover the first gate interconnect and the first drain interconnect.
Thus, a trigger voltage is reduced by a capacitance held between a first gate interconnect and a first drain interconnect. Therefore, a semiconductor device that can be easily conducted as a parasitic bipolar transistor can be obtained.
If the inventive method further includes the step g) of forming a second drain interconnect on the second interlevel insulating film so as to be electrically connected to the first drain interconnect, a semiconductor device connectable to the outside of the semiconductor device by a second drain interconnect can be obtained.
If in the inventive method, the thicknesses of the first drain interconnect and the first gate interconnect are larger than that of the second drain interconnect, a larger capacitance can be held.
If the inventive method further includes the step h) of forming a second gate interconnect on the second interlevel insulating film so as to be electrically connected to the first gate interconnect and have part facing part of the second drain interconnect, a larger capacitance can be held.
If the inventive method further includes, after the step h), the step j) of forming a third interlevel insulating film in which at least part is formed of a high dielectric material on the second interlevel insulating film, a larger capacitance can be held.
If in the step f), part of the second interlevel insulating film is formed of a high dielectric material, a larger capacitance can be held.
If the inventive method further includes the step i) of forming a first source interconnect on the first interlevel insulating film so as to be electrically connected to the source region and the distance between the first source interconnect and the first gate interconnect is greater than that between the first drain interconnect and the first gate interconnect, the distance between the first drain interconnect and the first gate interconnect is smaller than that in a known semiconductor device. Therefore, a capacitance can be more effectively held between the first drain interconnect and the first gate interconnect.